The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same. More particularly, the present invention relates to a technique which is effective if applied to a semiconductor integrated circuit device having a SRAM (Static Random Access Memory). The SRAM is disclosed, for example, in U.S. Pat. No. 5,194,749 which was filed by us at the U.S. Patent Office on Nov. 22, 1988 and given Ser. No. 274, 490.
The SRAM as a semiconductor memory device is equipped at the intersections between complementary data lines and word lines with memory cells, each of which is composed of a flip-flop circuit and two transfer MISFETs (Metal-Insulator-Semiconductor-Field-Effect-Transistors).
The transfer MISFETs of the memory cell have one of their source regions and drain regions connected with the input/output terminals of the flip-flop circuit and their other regions connected with the complementary data lines. Moreover, the transfer MISFETs have their gate electrodes connected with word lines so that their conductivity and non-conductivity are controlled by the word lines.
The flip-flop circuit of the memory cell is constructed as a data storage unit, which is composed of two driver MISFETs and two load MISFETS. One driver MISFET has its drain region connected with either the source region or drain region of one transfer MISFET and its source region connected with a reference voltage line. Moreover, this driver MISFET has its gate electrode connected with the source region or drain region of the other transfer MISFET.
The load MISFETS have their drain regions connected with either the source regions or drain regions of the transfer MISFETs and their source regions connected with the power source line. The load elements are formed over the driver MISFETs so as to reduce the area occupied by the memory cells thereby to improve the degree of integration. In the SRAM, a first conductive film formed on the main surface of a semiconductor substrate forms the gate electrodes of the driver MISFETs, and a second conductive film formed on the main surface of the semiconductor substrate forms the gate electrodes of the transfer MISFETs, the word lines to be connected with the gate electrodes and the reference voltage line to be connected with the source regions of the driver MISFETs. Moreover, a third conductive film formed over the first and second conductive films forms the gate electrodes of the load MISFETs, and a fourth conductive film formed over the third conductive film forms the channel regions, the source regions and the drain regions of the load MISFETs, and the power source line to be connected with the source regions of the load MISFETs.
In short, the SRAM, as disclosed in the above-specified U.S. Patent, adopts the so-called "complete CMOS structure", in which the flip-flop circuit of the memory cell is constructed to include the two driver MISFETs and the two load MISFETs so as to have its standby current reduced.
In order to eliminate the .alpha.-ray soft error of the memory cell, moreover, the SRAM is equipped with capacitance elements, in which the gate electrodes (i.e., the first conductive film) of the driver MISFETs are used as a first electrode and in which the gate electrodes (i.e., the third conductive film) of the load MISFETs formed on a dielectric film of an insulating film formed on the gate electrodes are used as a second electrode.